The final part of the 10 fundamental rules of high-speed PCB design focuses on board-level simulation encompassing signal integrity, crosstalk, and electromagnetic compliancy. Typically, a high-speed digital design takes three iterations to develop a working product. However, today, the product life cycle is very short, and therefore, time to market is of the essence. The cost per iteration should not only include engineering time but also consider the cost of delaying the products market launch. This missed opportunity could cost millions. Also, if an issue is not caught in the design phase and slips to through production and into the field, it could possibly damage a company’s reputation.
Unfortunately, simulation is often engaged towards the end of the design cycle. Ideally, the simulation should be done during the design process as part of standard practice. However, post-layout simulation is still necessary to validate the final signal and power integrity.
Board-level simulation cuts costs and a pre-layout simulation identifies issues in the conceptual stage so that they can easily be avoided. Post-layout simulation catches the issues during the design process, eliminating the potentially disastrous final stage changes.
VIII. Run the Post-layout Simulation
Simulate critical signals and match signal propagation and timing. Check for signal ringing and eye jitter.
The eye diagram is a common indicator of the quality of a signal in high-speed digital transmission lines. In an ideal world, eye diagrams would look like rectangular boxes. In reality, data transmission is imperfect, so the transitions of the bit pattern do not perfectly align on top of each other, and an eye-shaped pattern results. An open-eye pattern with little jitter (horizontal disparity) and noise (vertical deviation) is the objective.
To read this entire column, which appeared in the January 2019 issue of Design007 Magazine, click here.