Beyond Design: The Impact of Filled Vias on Thermal and Signal Integrity

The growing popularity of wide bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC) has enabled components to achieve higher operating temperatures and power outputs than silicon-based technology. However, this has not eliminated the need for careful thermal management to evenly distribute the heat generated to avoid the formation of dangerous hot spots and to minimize power losses. The heat generated by integrated circuits (Figure 1) poses great challenges, especially given today’s higher speeds, smaller board surface areas, and multiple devices populated on PCBs. These demands call for solutions to effectively dissipate the heat and ensure the performance and lifetime of the electronic system product. One solution is to use copper filled vias which complement thermal management, but how do filled vias affect signal integrity?

The conventional plating process cannot close the via completely—there is always an air gap in the middle. Thicker barrel plating improves the thermal transfer and current-carrying characteristics of vias at DC and low frequencies. IPC-4761 Design Guide for Protection of Printed Board Via Structures Standard covers via fabrication and protection. There are seven categories, but just three basic types:

  1. Tented via.
  2. Plugged via.
  3. Filled via.

All three via types can also be covered (on both sides); however, the filled via may also be capped. Capped vias are generally used for via-in-pad applications to prevent paste or resin flowing down the hole—the surface is planar and solderable. Typically, vias are plated over with electroless nickel immersion gold (ENIG). However, if via-in-pad is used, then ensure the connection to the planes uses thermal reliefs or you'll have a difficult time getting the device back up if it needs rework.

I have been tenting vias with either dry film or liquid photoimageable (LPI) solder mask for over 30 years. The basic reason is to seal the via hole for vacuum test fixtures and to prevent voids in the solder mask for silk-screening the component legend. Vias can be partially plugged with non-conductive paste but there is a chance of cracks from encapsulated gas during soldering. Or they can be filled with non-conductive or conductive materials.

Proper thermal management is necessary to keep each component within safe temperature limits. The junction temperature should never exceed the limit indicated in the manufacturer’s datasheet (generally between 125–175°C for silicon-based devices). The heat generated by each component is transferred to the outside through the package and the pins. The two main techniques used to improve PCB thermal management consist in the creation of large ground planes and in the insertion of thermal vias. Thermal vias are used to transfer heat from one layer to another. Unfortunately, FR-4 does not offer high thermal transfer.

Copper-filled thermal vias provide an efficient heat dissipation path directly incorporated into PCBs with placement directly under a surface-mounted IC (the heat source). This allows direct surface mount bonding for maximum heat transfer using surface mount copper material. Specialized materials such as Kuprion’s copper thermal via paste are capable of filling vias of at least 5 mm in diameter. When fused, the copper paste converts to solid copper without melting, which provides thermal conductivities in the range of approximately 110-180 W﮲m-1﮲K-1 (watts per meter-Kelvin) and up to 290 W﮲m-1﮲K-1 for microvias (up to 25 mil in diameter).

Engineers have debated the merits of hollow vias vs. solid vias for RF performance. There is a great temptation to believe that making the via solid will somehow reduce the equivalent inductance of the structure. However, once the skin-effect kicks-in, in the megahertz range, then the current tends to only flow in the perimeter of the barrel.

Conductive epoxy-filled is the best practice for the vias to have a finished diameter between 8–18 mil. This allows the epoxy—conductive or non-conductive—to be pushed through the hole completely, but not to run out. The associated aspect ratio is best if the depth-to-diameter is less than 10:1.

A plate-shut process provides greater reliability for microvias, as opposed to filling with non-conductive ink and then plating over. Filling vias creates a solid core. This allows for a flat surface to be plated, and keeps the solder at the assembly level from leaking through and compromising the solder joint. This provides for the most reliable finished assembly.

The following materials can be used to ensure vias are sealed when filled:

  1. A special plugging resin (e.g., Taiyo THP-100 DX1 thermally curable permanent hole-filling material) is suitable for plated through-hole and via-in-pad applications.
  2. Copper: Classic copper via filling methods involve using pure copper to fill the hole.
  3. Silver conductive epoxy resin: This is an alternative for filling vias but is expensive and copper works more effectively (e.g., DuPont CB100 or Tatsuto AE3030 screen-printed material).

PCBs that have copper-filled vias will stand up to the conditions presented by high power, radio frequency, microwave, and LED applications. The high-power integrated circuits that run these types of PCBs use currents that a copper-filled via can withstand, but not a plated through-hole.

A complete view of the current distribution can be visualized using a 3D solver. Figures 2 and 3 present three views of the conduction current at 18 GHz on a microstrip, hollow via, and solid via using Flomerics Micro-Strips, a 3D TLM solver: a) perspective view; b) top view of strip and ground plane; and c) bottom view of top strip. The scale in all three plots is 0 to 120 nA/m.

In both the hollow and solid barrel cases, the current is clearly flowing on the near side of the via barrel. There is also a small amount of current that flows down the inside surface of the via barrel. The return current in the ground plane can also be seen in Figures 2a and 3a. We tend to forget that microstrip is a two-conductor system—the return path is just as important as the signal path. Figures 2b and 3b show a top view of the complete structure. Note the non-uniform current distribution across the width of the strip. Finally, in Figures 2c and 3c, there is a view of the bottom side of the top strip.

Comparing the last two views we note that there is more current on the bottom side than the top side of the trace. At low frequencies, the current would split more or less equally between the top and bottom surfaces of the strip. But, as frequency increases, the current distribution shifts toward the bottom side of the strip due to the proximity effect. The current distribution of the hollow and solid barrel has not changed significantly at 18 GHz, although this would be quite different at DC. The equivalent inductances for the hollow via and solid via cases are virtually identical. At 18 GHz, skin depth effects alone will force the current to the surface of the solid via.

Filled vias have little impact on signal integrity at high frequency. However, there is a definite benefit in using filled vias if thermal relief is the goal. At DC, filled vias also provide increased current capacity but at 18 GHz both filled and hollow vias perform much the same.

Key Points

  • Copper-filled vias complement thermal management.
  • The conventional plating process cannot close the via completely.
  • Thicker barrel plating improves the thermal transfer and current-carrying characteristics of vias at DC and low frequencies.
  • Thermal vias are used to transfer heat from one layer to another.
  • FR-4 does not offer high thermal transfer.
  • Solid vias do not reduce the equivalent inductance of the structure. The current tends to only flow in the perimeter of the barrel due to the skin effect.
  • Conductive epoxy-filled is the best practice for the vias to have a finished diameter between 8–18 mil.
  • Filling vias creates a solid core and allows for a flat surface to be plated. This keeps the solder at the assembly level from leaking through and compromising the solder joint.
  • The equivalent inductances for the hollow via and solid via cases are virtually identical.
  • At 18 GHz, skin depth effects alone will force the current to the surface of the solid via.


Beyond Design: The Proximity Effect, by Barry Olney, Design007 Magazine, March 2019.

“Microwave Circuit Modeling using Electromagnetic Field Simulation.” D. Swanson and W. Hoefer, Guide to Copper-Filled Vias, Process & Benefits. 

Copper & Epoxy Filled Vias, Cirexx International.

“High-Power Dissipation Copper Filled Thermal Vias by Kuprion,” Power Electronics News, April 23, 2021.

 This column originally appeared in the November 2021 issue of Design007 Magazine.



Beyond Design: The Impact of Filled Vias on Thermal and Signal Integrity


The growing popularity of wide bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC) has enabled components to achieve higher operating temperatures and power outputs than silicon-based technology. However, this has not eliminated the need for careful thermal management to evenly distribute the heat generated to avoid the formation of dangerous hot spots and to minimize power losses. The heat generated by integrated circuits poses great challenges, especially given today’s higher speeds, smaller board surface areas, and multiple devices populated on PCBs.

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Beyond Design: Crosstalk Margins


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10 Fundamental Rules of High-Speed PCB Design, Pt. 1


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DDR3/4 Fly-by Topology Termination and Routing


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Beyond Design: Common Symptoms of Common-Mode Radiation


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Beyond Design: A Review of HyperLynx DRC


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Beyond Design: AC/DC is Not Just a Rock Band


Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

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The Target Impedance Approach to PDN Design


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Beyond Design: When Do Traces Become Transmission Lines?


At low frequencies, traces and components on a PCB behave simply as lossless lumped elements—as taught in Circuit Theory 101. But as the frequency increases, the copper trace and adjacent dielectric(s) become a transmission line, the skin effect forces current into the outer regions of the conductor and frequency dependant losses impact on the quality of the signal. The PCB trace now behaves as a distributed system with parasitic inductance and capacitance characterized by delay and scattered reflections. The behavior we are now concerned about occurs in the frequency domain rather than the familiar time domain. This is the real world of high-speed design.

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Beyond Design: Plane Cavity Resonance


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Beyond Design: When Legacy Products No Longer Perform


As IC die sizes continue to compact due to demand for smaller and faster technology, and as switching speeds continue to improve, rise and fall times are creeping down into the sub-nanosecond realm, a territory previously reserved for microwave engineers. It is a common quandary that established products that have worked flawlessly for years suddenly stop performing reliably, due to a new batch of ICs that is used in the latest production run.

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Beyond Design: Transmission Line Losses


In an ideal world, the entire signal waveform would uniformly decrease in amplitude, over distance, and the rise time would remain constant. This reduction in amplitude could easily be compensated for by applying gain (cranking up the volume) at the receiver. However, as signals propagate along a lossy transmission line, the amplitude of the high-frequency components is reduced, in magnitude, whereas the low-frequency components are unaffected. This selective attenuation of high-frequency components is the root cause of ISI and collapse of the signal eye.

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Beyond Design: FPGA PCB Design Challenges


The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expedite the PCB layout. Hundreds of logical signals need to be mapped to the physical pin-out of the device, and they must also harmonize with the routing requirements whilst maintaining the electrical integrity of the design.

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Beyond Design: The Dark Side–Return of the Signal


I guess we all think of a copper plane as a thick, solid plate of copper that can basically handle any amount of current we sink into it. It also serves to make the circuit layout easier, allowing the PCB designer to ground anything, anywhere without having to run multiple tracks. That may well be the case with DC or very low-frequency analog circuits, but certainly not in the case of high-speed design.

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Beyond Design: Return Path Discontinuities


PCB designers generally take great care to ensure that critical signals are routed exactly to length from the driver to the receiving device pins, but take little care of the return current path of the signal. Current flow is a “round trip” and the critical issue is delay, not length. If it takes one signal longer for the return current to get back to the driver—around a gap in the plane for instance—then there will be skew between the critical timing signals. Return path discontinuities (RPDs) can create large loop areas that increase series inductance, degrade signal integrity and increase crosstalk and electromagnetic radiation.

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Beyond Design: Microstrip Coplanar Waveguides


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New Functionality Improves Designer’s Productivity


I originally came up with the concept of an online impedance calculator way back in 1994 when I was working on the PCB layout and design for a new generation of SPARC 20 servers. We basically reformatted a Sun SPARC 20 pizza box motherboard to fit into a 5.25-inch drive slot.

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Beyond Design: PDN–Decoupling Capacitor Placement


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Beyond Design: Uncommon Sense


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Beyond Design: Rock Steady Design


How do we ensure that our high-speed digital design performs to expectations, is stable given all possible diverse environments, and is reliable over the product’s projected life cycle? For the perfect transfer of energy and to benefit from the highest possible bandwidth, the impedance of the driver must match the impedance of the transmission line and be constant along its entire length.

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The Rise of the Independent Engineer


With the changing demographics, the old-timers in our industry—the master PCB designers—are about to retire and hand over the exacting job of PCB design to the Gen-X and Ys. These generations, shaped by technology, will tackle the most demanding designs without possessing the experience that we veterans benefit from. And to top it off, these up-and-coming designers will be degreed engineers who have to cope with both design and layout tasks as the specialized PCB designer’s positions are phased out.

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The Case for Artificial Intelligence in EDA Tools


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Beyond Design: The Need for Speed—Strategies for Design Efficiency


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Beyond Design: Plane Crazy, Part 1


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Why Autorouters Don’t Work: The Mindset!


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Beyond Design: Stackup Planning, Part 4


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Beyond Design: Stackup Planning, Part 3


Following on from the first Stackup Planning columns, this month we will look at higher layer-count stackups. The four- and six-layer configurations are not the best choice for high-speed design. In particular, each signal layer should be adjacent to, and closely coupled to, an uninterrupted reference plane, which creates a clear return path and eliminates broadside crosstalk. As the layer count increases, these rules become easier to implement but decisions regarding return current paths become more challenging.

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Beyond Design: Stackup Planning, Part 2


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Beyond Design: Stackup Planning, Part 1


The PCB substrate that physically supports the components, links them together via high-speed interconnects and also distributes high-current power to the ICs is the most critical component of the electronics assembly. The PCB is so fundamental that we often forget that it is a component and, like all components, it must be selected based on specifications in order to achieve the best possible performance of the product. Stackup planning involves careful selection of materials and transmission line parameters to avoid impedance discontinuities, unintentional signal coupling and excessive electromagnetic emissions. Barry Olney explains.

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Controlled Impedance Design


Controlled impedance—it’s all about transmission lines. For perfect transfer of energy, the impedance of the driver must match the transmission line. A good transmission line is one that has constant impedance along the entire length of the line, so that there are no mismatches resulting in reflections. But unfortunately, drivers do not have the exact impedance to match the line (typically 10–35 ohms) so terminations are used to balance the impedance, match the line and minimize reflections.

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Beyond Design: Learning the Curve


Currently, power integrity is just entering the mainstream market phase of the technology adoption life cycle. The early market is dominated by innovators and visionaries who will pay top dollar for new technology, allowing complex and expensive competitive tools to thrive. However, the mainstream market waits for the technology to be proven before jumping in. Power distribution network (PDN) planning was previously overlooked during the design process, but it is now becoming an essential part of PCB design. But what about the learning curve? The mainstream market demands out-of-the-box, ready-to-use tools.

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Split Planes in Multilayer PCBs


Creating split planes or isolated islands in the copper planes of multilayer PCBs at first seems like a good idea. Today’s high-speed processors and FPGAs require more than six or seven different high-current power sources. And keeping sensitive analog circuitry isolated from those nasty, fast, digital switching signals seems like a priority in designing a noise-free environment for your product. Or is it?

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Effects of Surface Roughness on High-Speed PCBs


At frequencies below 1GHz, the effect of copper surface roughness on dielectric loss is negligible. However, as frequency increases, the skin effect drives the current into the surface of the copper, dramatically increasing loss. When the copper surface is rough, the effective conductor length extends as current follows along the contours of the surface up and down with the topography of the copper surface.

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Signal Integrity, Part 2


In Part 1 of his signal integrity series, Columnist Barry Olney examined how advanced IC fabrication techniques have created havoc with signal quality, and radiated emissions. Part 2 covers the effects of crosstalk, timing, and skew on signal quality.

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Signal Integrity, Part 1 of 3


As system performance increases, the PCB designer’s challenges become more complex. The impact of lower core voltages, high frequencies, and faster edge rates has forced us into the high-speed digital domain. But in reality, these issues can be overcome by experience and good design techniques. If you don’t currently have the experience, then listen-up.

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Material Selection for Digital Design


In his latest column, Barry Olney looks at what types of materials are commonly used for digital design, and how to select an adequate material to minimize costs. He advises, "Of course, selecting the best possible material will not hurt, but it may blow out the costs."

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Beyond Design: Concurrent Design


Concurrent design is the practice of developing products in which the different stages run simultaneously rather than consecutively. It decreases product development time and also time-to-market, leading to improved productivity and reduced costs. The practice is a relatively new process strategy and although the initial implementation can be challenging, the competitive advantage means it is beneficial in the long term.

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Surface Finishes for High-Speed PCBs


PCB surface finishes vary in type, price, availability, shelf life, assembly process, and reliability. While each treatment has its own merits, electroless nickel immersion gold (ENIG) finish has traditionally been the best fine pitch (flat) surface and lead-free option for SMT boards over recent years. But, unfortunately, nickel is a poor conductor with only one third the conductivity of copper.

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Beyond Design: Transmission Line - From Barbed Wire to High-speed Interconnect


Contrary to common belief, the transmission line does not carry the signal itself but rather guides electromagnetic energy from one point to another. It is the movement of the electromagnetic field or energy, not voltage or current that transfers the signal. The voltage and current exist in the conductor, but only as a consequence of the field being present as it moves past.

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Mythbusting: There are No One-way Trips!


One of the greatest myths in PCB design is that we only have to route signal traces from pin-to-pin to make a complete connection. And, that ensuring these traces have matched delay is the only timing issue we need to consider. However, current is not a one way trip--it must complete the circuit back to the source to provide the round-trip current loop.

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Matched Length Does Not Always Equal Matched Delay


In previous columns, Columnist Barry Olney has discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month's column he takes a look at the actual differences between the two.

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Beat the Traffic Jam - Effective Routing of Multiple Loads


In a previous column, Barry Olney discussed various termination strategies and concluded that a series terminator is best for high-speed transmission lines. But, what if there are a number of loads--how should these transmission lines be routed? For perfect transfer of energy and to eliminate reflections, the impedance of the source must equal the impedance of the trace(s) to the load.

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PDN Planning and Capacitor Selection, Part 2


In Part 1 of this column, Barry Olney looked closely at how to choose the right capacitor to lower the AC impedance of the power distribution network (PDN) at a particular frequency. This month he continues from there looking at the one-capacitor-value-per-decade and optimized value approaches.

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Beyond Design: Entanglement - The Holy Grail of High-Speed Design


While high-speed SERDES serial communications seems to currently be at the cutting edge of technology, maybe it will shortly become an antiquated low-speed solution--even speed-of-light fiber optics may become obsolete. This month, Columnist Barry Olney looks at how quantum physics is transforming our world and how it could affect PCB design.

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Beyond Design: Impedance Matching: Terminations


The impedance of the trace is extremely important, as any mismatch along the transmission path will result in a reduction in signal quality and possibly the radiation of noise. Mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the load.

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Material Selection for SERDES Design


Many challenges face the engineer and PCB designer working with new technologies. For SERDES--high-speed serial links--loss, in the transmission lines, is a major cause of signal integrity issues. Reducing that loss, in its many forms, is not just a matter of reducing jitter, bit error rate (BER) or inter-symbol interference (ISI).

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Beyond Design: Practical Signal Integrity


"If you are a digital designer, you will eventually have SI problems whether you like it or not. But all is not lost. If you learn to work with these issues, then you will soon become proficient with high-speed design," says columnist Barry Olney.

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Beyond Design: Design for Profit


Design for profit (DFP) is gaining more recognition as it becomes clear that the cost reduction of printed circuit assemblies cannot be controlled by manufacturing engineers alone. The PCB designer now plays a critical role in cost reduction, says columnist Barry Olney.

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Beyond Design: Skewed Again


Differential skew has become a performance limiting issue for high-speed SERDES links. The operation of such links involves significant amounts of signal processing to recover clocks, reduce the effects of high-frequency losses, reduce inter symbol interference, and improve signal-to-noise ratio.

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Beyond Design: Losing a Bit of Memory


No matter what type of memory used in a design, the clock should always have the longest delay. This ensures that the other signals have time to settle before the clock arrives at the device and samples the bus.

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Beyond Design: Electromagnetic Fields, Part 2


In his last column, Barry Olney discussed how magnetic fields revolve around the earth and how these fields are also present in a multilayer board. Part 2 of "Electromagnetic Fields" will look at how the phenomena influence transmission lines and how they can be applied in a BEM field solver.

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Beyond Design: Electromagnetic Fields, Part 1


Our whole world literally revolves around electromagnetic fields. Columnist Barry Olney says much insight into high-speed PCB design can be gained by understanding the behavior of transmission lines and the influence of their associated electromagnetic fields.

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Beyond Design: Postmortem Simulation


Developing the practice of performing a post-mortem analysis on every project facilitates a culture of continuous improvement. This embedded culture of ongoing, positive change is the best way to ensure long-term success according to Barry Olney.

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Beyond Design: Mixed Digital-Analog Technologies


The key to a successful mixed digital-analog design is functional partitioning, understanding the current return path, routing control and management, and using a common ground plane. Barry Olney takes us into the mix this week.

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Beyond Design: Pre-Layout Simulation


Pre-layout simulation allows a designer to identify and eliminate signal integrity, crosstalk and EMC issues early in the design process. This is the most cost-effective way to design a board. Barry Olney explains why in this case, sooner is better than later.

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Beyond Design: Power Distribution Network Planning


The power distribution network (PDN) of a multilayer PCB should distribute low noise and stable power to ICs over the entire board area. Ideally, the AC impedance, between power and ground, should be zero, up to the maximum operating frequency for reliable performance.

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Intro to Board-Level Simulation and the PCB Design Process


Board-level simulation reduces costs by identifying potential problems at the conceptual stage, so that they can easily be avoided, and then catching any further issues during the design process, eliminating the potentially disastrous final-stage changes. By Barry Olney.

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Board-Level Simulation and the Design Process: Plan B - Post-Layout Simulation


Post-layout simulation covers batch mode simulation, which automatically scans nets on an entire PCB, flagging signal integrity, crosstalk and EMC hot spots. While post-layout simulation can be used for disaster recovery, ideally this process is completed during the design process. Barry Olney explains.

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Beyond Design: A New Slant on Matched-Length Routing


This month, Barry Olney discusses the traditional serpentine routing for matched length signals and looks at a potentially desirable alternative, the octagonal spiral pattern, that can be especially useful if real estate is at a premium.

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Beyond Design: Controlling the Beast


In this column, we will tackle the "microstripum crosstalkus radiarta," an insidious little creature more commonly known as microstrip crosstalk radiation. Thriving on the outer layers of PCBs, crosstalk, like fleas on a dog, can't be eliminated completely or forever; the key is learning how to minimize and control it.

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Beyond Design: Embedded Signal Routing


Is radiation actually attenuated when high-speed signals are routed embedded between the planes? There are specific constraints and factors to consider when assessing just how much attenuation we actually get from embedding the high-speed signals between the planes. Barry Olney breaks it all down.

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Beyond Design: The Dumping Ground


By definition, a ground plane in a PCB is a layer of copper that appears to most signals as an infinite ground potential. This month, we discuss best practices for selecting reference planes and routing pairs for high-speed designs on multilayer boards.

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Beyond Design: Controlling Emissions and Improving EMC


Unintended noise can be a formidable enemy, and it is best to totally eliminate, control or attenuate the emissions at the source. Controlling the impedance of the substrate and terminating the transmission line to match the impedance of the respective source and load significantly reduces radiated noise, virtually eliminating the noise at the source.

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PCB Design Techniques for DDR, DDR2 & DDR3, Part 2


This second and final part in a series examining PCB design techniques will look at a comparison of DDR2 and DDR3, DDR3 design guidelines, pre-layout analysis, critical placement, design rules, and post-layout analysis.

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