The Bare (Board) Truth: I'm From CAM and I'm Here to Help

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Robert Burns once opined, “The best laid plans of mice and men often go awry.” And so it goes. Once again, this column will reiterate the basics about what designers need to do to control impedances.

I know that I’m beating this topic to death, but a recent experience dictates that I once again revisit the issue of controlled impedances and what is, or is not, called out on the drawing.

Not long ago, a longstanding customer had a design re-spin. It happened to be a high layer-count board that previously had controlled impedance. This particular story goes all the way back to the original design and prototyping of this product overseas.

The original design came in with a standard note about controlled impedances that said it all: The size of the traces being controlled, where they resided, and the threshold and tolerance they were to be, along with a proposed stack-up and standard allowance to be able to either resize traces or dielectrics to achieve the desired impedances. Fair enough. The job goes though the shop and ships along with Impedance test results.

A few weeks later, the customer needs a re-spin. This time no notes exist regarding any impedances, but amazingly, the precise stack-up we used last time was now put on the drawing. As you all know, this is not something I advise. A fabricator’s stack-up is the literal work stack-up being used. Not all fabricators incorporate a “nesting” value between layers, so a dielectric listed as, say .0074” may really press out to be .0068-.0069” depending on the layer interfaces.

By this, I mean:  Are they mainly copper as full planes? In that case, they may stay close to the .0074” in this example. Are they split planes? In that case, they may press slightly thinner to fill the porous areas around the metal on that layer.

Or are they pure signal layers? In that case, they may press out even thinner yet. For these reasons I do not recommend including a fabricator’s stack-up on the drawing. A fabricator’s stack-up that accounts for all the layer-nesting can often be worse if your fabricator is not careful and uses those figures as numbers prior to any pre preg nesting. But I digress...

Remember, the latest design is released without any notes regarding any controlled impedances, but now the drawing features the same stack-up used on a previous version. Then, a pure coincidence occurs in CAM during analysis of the latest design. Some gap violations on external layers that go below our current process minimums for the copper weight specified are due to a shift or offset in the surrounding copper pour. We contact the customer about the violations.

Did I mention that this part is an expedite?

Some hours go by before the customer responds with, “We see no such violations on our end. We have looked at both the design settings and the exported Gerbers and we suspect your software.” Additionally, the customer hesitated to change the outer layer starting copper weight to deal with the smaller gaps as it may affect the impedances.

OK, forget that we have been in business for years using this same CAM software package and have had no such issues at the analysis stage. The customer is always right. Indulge the customer. Another analysis is run with a completely different software package. Same results.

This time, more specific regions are identified so the customer can observe these violations. This time the customer comes back with, “Our apologies, we do see the violations, and we will work on getting you some new files.”

At this point, we are obligated to ask about the impedances as they were not called out on the drawing. To which the customer replies, “We thought if we merely spec out your specific dielectrics, we would not have to call out any controlled impedances, and frankly, we would prefer to control them on our end anyway.” ‘Nuff said.

At this point, we remind our customer that on the previous part with controlled impedances, the note allowed us to resize traces or dielectrics to achieve the desired impedances. We ended up doing a little of both, so merely adding a specific dielectric note will not get them what they need for the impedances. 

I reiterate what all fabricators really need in this respect: “What sizes are being controlled? On what layers do they reside (The customer could be using a trace size that is being controlled on one layer but not on another)? What is the threshold - 50 ohms, 90 ohms, 100 ohms?”

Believing this to be understood, we moved forward, with the customer agreeing to send new artwork and a new drawing specifying impedances. Upon receipt of the new artwork and drawing, we conduct our normal pre-engineering review prior to CAM.

Now notes regarding impedances are included, but they are incomplete or wrong.

The first note reads, “All signal layers to be 50 ohms.” This does not tell the fabricator what size is being controlled. The second and third notes had typos showing different line and space combinations as all on external layers (presumably, one of the two notes was intended to focus on inner layers) and two of the four trace sizes described did not even exist.  At this point we were once again obligated to contact the customer.

The customer is none too happy with a further delay of this expedite multilayer, and he is quite vocal in letting us know this. We had come back at them with about five questions, some related to the fact that things were not the same as the previous design in regards to the impedances’ locations, and that many of the trace sizes now being called out do not exist. Ultimately, we are attempting to do due diligence, but it was evident this experience was looked upon by the customer as invasive. After a long dissertation on why they want us to simply build the part as previously specified and that they do not want a board shop’s assistance in impedance control, we politely say, “No problem.”

Some of our questions are still unanswered, so we once again posed them at the risk of further agitating the customer. This time we took this approach: “Can we safely assume the 50 ohm signals are on layers X, Y and Z and that the trace size being controlled is W? Can we safely disregard any notes about any differential trace sizes that do not exist?”

Given their responses, we move forward and finally build the part for the customer.

So, what have we learned from this experience? (Other than seeing firsthand evidence that you can lead a horse to water but you can’t make him drink.) Well, perhaps we have learned that not all fabricators are meddling in your design and some of us really do want to help to make it right the first time.

We have also learned that patience and perseverance can go a long way in aligning yourself with the customer! As always, I appreciate your time. If you have any comments or questions, feel free to contact me.

Mark Thompson is in engineering support at Prototron Circuits. To contact Mark, click here, or call 425-823-7000.


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