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Seasons greetings all! In this column, I will discuss what designers may want vs. what fabricators may need.
I’ll start with material selection. Many designers lately are asking for low-resin, high-glass pre-pregs as interfaces for impedance designs. This is understandable from their standpoint, because the Dk is higher and the glass weave is wider. This works well for differential pair performance, but it is sometimes difficult from a fabrication standpoint. Let me give you an example:
Let’s say the customer is dictating the use of 7628 or 7629 type pre-preg plies in an effort to keep the pre-preg Dk above 4.0, and the dielectrics in the stackup call for a single ply of 7628 to achieve required impedances. Because this ply is predominantly glass and less resin, the potential for resin starvation at lamination (depending upon the layer interface – GND, SPLIT, SIGNAL) is high. This ply is typically avoided by the fabricator in favor of one of equal dielectric value, one composed of more plies of a more resin-rich material. But doing so generally requires the fabricator to tweak the lines/spaces to deal with the lower DK of the more resin-rich materials.
This was more of an issue when fabricators were using FR-4 flavors, because the dielectric constant swing from resin-rich material to less resin-rich was a greater percentage. As an example, even the high-temp FR-4 types went from an approximation of 3.3 Dk for 106 pre-pregs to 4.7 for thicker cores.
Some of today’s material alternatives have less deviation across the board, so-to speak.
For example, ITEQ’s IT-180 or IT-180A is approximately 4.1 Dk for the resin-rich plies like 106, and up to 4.5 for thicker cores. Many designers still use an approximation for calculating impedance (yes, this is true), and many designers assume when literature says the Dk will be 4.5 at 1 gig, they can model all impedances as such. But many times they do not notice the Dk value expressed is for a core .018” or thicker, where the core make-up DOES use more glass-rich pre-preg plies.
Of course the reality is that today’s lack of board real estate means more layers and finer lines. Finer lines typically mean less dielectric between ref planes and therefore a lower Dk preg or core. If a case like the one stated above, it is critical to meet with your fabricator to review the impedances at the earliest possible point.
If you know me at all you know I write most of my columns relative to controlled impedance. Over the last 10 years many of our customers have specified either dielectrics in a stack-up or a specific Dk value or both, but with NO information about any controlled Impedances they may have.
I understand the engineer’s need to control as many aspects as he can but not including information about impedances is not prudent in my book. Well over 70% of our customers that have merely specified a dielectric distance on a stack-up come back saying, “Yes, there are impedances” and provide the information necessary for calculations and stack-up generation. This includes what sizes are being controlled, on what layers and the threshold and tolerance.
Sometimes what is needed is for the fabricator to model the impedance using the specific parameters described by the customer side by side to show they do not always jive with their initial calculations. We use a Polar field solver. A field solver is much more than a simple calculator. It allows us to skew for over-plate, under-plate, over-etch, under-etch, too much mask, too little mask, etc. But I digress.
There are times when specific dielectrics are just that, meaning they are specific to deal with issues like dielectric separation for maximum isolation on high-current jobs, or minimum dielectrics between, say, power and GND planes for decoupling purposes. As fabricators we are simply doing due diligence when we ask if any impedances are involved on jobs with specific dielectrics but without callouts for impedances. Many times, we see the signs of impedances that also prompt questions. These are things like obvious differential pairs or single ended serpentine traces that scream impedance control.
Perhaps as few as 10% of the customers we ask about impedances (when they’re not called out) have designs in which the calculated dielectric jives with the predicted values. Again, all the more reason to ask your fabricator to run calculations and propose a build at the earliest possible time.
Many times deviations from what is expected vs. the reality of the situation can come from misunderstandings about impedance modeling parameters. Many customers forget to assume the 8/10 to 1 mil plate-up for outer layers on top of the starting copper weight. I have seen many calculations assuming 1.4 mils TOTAL surface copper. Remembering the total copper is the base copper plus the plate-up, so even starting on QUARTER ounce foils results in approximately 1.8 mils of total copper. Again, this mismatch can be as much as a 3-4 ohm difference in predicted vs. actual.
In addition, starting on quarter ounce foils typically means the lines sizes for the desired impedances have to be increased, and with today’s tight geometries sometimes this is not possible.
Another common issues with customer-modeled vs. fabricator-modeled impedances is that most customers use a calculator that does not allow for the difference between the crest and the foot of a given trace. Again, with smaller geometries of .1 mm and less, even this small amount of etch deviation can sometimes manifest itself as much as 1-2 ohms between customer-predicted vs. fabrication reality.
While we are on the subject, let’s talk a little bit about reference planes. From a fab viewpoint, ANY metal above or below an intended impedance trace acts as a reference plane. Many jobs that were intended to be dual asymmetric striplines end up as offset striplines after copper pour has been added to the layers. As an example of this, let’s say layers 3 and 4 of a 6-layer are designed and trace-compensated for dual asymmetric striplines using layers 2 and 5 as reference planes, but then the engineer asks the designer to add poured copper on all layers to minimize electrical emissions. And by doing so, he has created situations where some of the traces are now ref layers above and below the intended Impedance traces.
Similarly, unintentional coplanar coupling is sometimes induced when this copper pour is added. Again the impedance may have originally been set up for “free space” dual asymmetric strip-lines and now is an offset stripline and coplanar coupled due to the proximity of the copper pour to the impedance traces.
Bottom line, do the research at the engineering stage prior to trace layout. Get calculations and proposed builds from a few different fabricators so that your designs require the least amount of tweaking and therefore are reproducible no matter where you go.
As always I really appreciate your time. If you have any comments, questions or concerns, feel free to contact me.
Until next month, thanks again!
Mark Thompson is in engineering support at Prototron Circuits. To contact Mark, click here, or call 425-823-7000.