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You are a backplane designer and have been assigned to engineer a new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s on Day One and be 10GB/s ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.
You come up with a concept you think will work, but the backplane will be thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.
You are worried about the size and design of the differential via footprint used for these connectors because you want to maximize the routing channel through the connector field. This requires you to shrink the anti-pad dimensions so the tracks will be covered by the reference planes. But you can’t easily quantify the consequences to the via of doing so.
You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of non-functional pads on the inner layers and planning to back-drill the connector via stubs will help, but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night, is to put in the numbers.
So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before: For high-speed, the best way to model a via is with a 3D electromagnetic field solver. Although this might be true, what if you don’t have access to such a tool, because they cost more than your company wants to spend, or because you don’t have the expertise or the time to learn how to build a model you can trust to make a timely decision?
Furthermore, 3D field solvers typically produce S-parameter behavioral models. Since they represent only one sample of a given construction, it is impossible for you to perform what-if, worst-case, min/max analysis with a single behavioral model. Because of this, many iterations of the model are required, causing further delay in getting your answer.
A circuit model, on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst-case analysis can be explored quickly and easily.
In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.
Now there is another way. As I promised you in my last column, “The Three Amigos: Twin-Rod, Rod-Over-Plane and Coax,” I will reveal how you can call on these newfound friends to develop equations, to help you calculate the parameters of a practical differential via circuit model.
Differential Via Structure Anatomy
To begin with, let’s start with an example of a differential via structure as shown in Figure 1. It is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.
Figure 1. Differential via structure through a multilayer PCB.
The via barrel is a plated through-hole extending the entire length of a PCB stack-up. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Anti-pads are the clearance holes in the plane layers that allow the via barrel to pass through them without shorting.
The through portion of the via is the length of the barrel connecting one signal layer to another and is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB.
Building a Simple Scalable Circuit Model
On close examination of Figure 2, a differential via structure can be represented by a twin-rod transmission line geometry. The magnetic field loops, defining the odd-mode inductance of each via, is shown in blue. The electric field, as shown in red, is represented by excess capacitance distributed over its entire length. Smaller anti-pad diameters lead to higher excess capacitance; which results in lower via impedance; thereby causing higher reflections.
In all high-speed serial link designs, it is common practice to remove all non-functional pads and to maximize the anti-pad clearance as much as practically possible. Oval anti-pads are often used in this regard to further mitigate excess via capacitance.
Figure 2. Differential via resembles a twin-rod transmission line structure. The magnetic field loops defining the odd-mode inductance of each via is shown in blue, while the electric field is represented by excess capacitance between the via barrel and anti-pad as shown in red.
Figure 3 illustrates the equivalent circuit model for a differential via that could be used in a channel topology circuit simulation. Here, it is modeled with Agilent ADS software using a coupled line transmission line model for each section, but any equivalent Spice-like circuit simulator will do. This model can be integrated in any channel simulation scenario and scaled for any combination of layer transitions, impedance and delay.
Figure 3. Equivalent circuit model of a differential via modeled in ADS.
Since the cross-section of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.
When driven differentially, the odd-mode parameters of each via are of major importance. Since the even-mode parameters have no impact on differential performance, both odd-mode and even-mode parameters are set to the same values in the model.
The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia) of a differential via structure, and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.
Developing the Equations
Anti-pads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square or rectangular variations (not shown) are similar.
Figure 4. Typical round/oval anti-pad variations of a differential via structure. Square/rectangular anti-pads (not shown) are also used.
Referring back to Figure 2, we see each via of a differential pair looks a lot like two coaxial transmission line structures with the inner layer reference planes acting as the shield. Electrostatically this is a good approximation. But because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twin-rod structure.
So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the odd-mode impedance representing Zvia.
For inductance, we use the odd-mode inductance formula from the twin-rod transmission line geometry to calculate Lviaas defined by Equation 1.
s = Via–via pitchr = Drill radius Len = Via length (inches)
Referring to Figure 4, we then calculate the odd-mode capacitance for Cvia using Equation 2. It is derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, Microwave Transmission Line Impedance Data. In the original formula, both the shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the anti-pads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t]; which is the denominator in the standard Coaxequation.
Since conventional FR-4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. What this means is the dielectric constant of the material surrounding the via hole structure (Dkxy), can be 15-20% higher than the bulk dielectric constant from data sheets (Dkz) surrounding a trace, as in stripline construction.
Now that we have defined Lvia, Cvia and Dkavg,we can estimate Zvia using Equation 3.
But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarter-wave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s odd-mode impedance has decreased due to the distributed capacitive loading of the anti-pads.
To help us with this task, we start with the twin-rod formula. The odd-mode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:
By substituting Equation 3for Zodd into Equation 4 and solving for Dkeffwe eventually come up with Equation 5.
Validating the Model
A simple 26-layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs were measured using an Agilent N5230A VNA.
The differential vias had the following common parameters:
Via drill diameter; D = 28 mils Center to center pitch; s = 59 mils Oval anti-pads= 53 mils x 73 mils Dk of the laminate = 3.65 Anisotropy in Dkxy = 18% Zvia = Zstub = 31.7 Ohms (per Equation 3) Dkeff = 6.8 (per Equation 5)
The topology circuit model of the test vehicle is shown in Figure 5. The top half is the measured channel using an S-parameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the S-parameter and TDR results.
Figure 5. Circuit topology model of test vehicle. Top half is measured 4-port S-parameters and bottom half is equivalent circuit model.
The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this practical modeling technique is summarized in Figure 6. The insertion loss plots (SDD21), in the frequency domain, are shown on the left, while the TDR plots (TDD21) are shown on the right.
The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub length, the lower the resonant frequency null. If this null happens at, or near the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we back-drill stubs after the board has been fabricated.
The simulation correlation is excellent up to about 12-14 GHz. The TDR plots show excellent impedance matching and delay for all three cases; while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.
Figure 6. Measured (red) vs simulated results (blue) of long, medium and short via stub.
As illustrated, a simple twin-rod model (Figure 2) is used as the basis for a practical differential via circuit modeling technique. By using Equation 3and Equation 5, you can quickly determine the odd-mode impedance and effective dielectric constant needed for the circuit model of Figure 3.
Of course, you should only use this methodology as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worthwhile to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.
On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.
Try it the next time you are losing sleep over your design challenges.
1. L. Simonovich, E. Bogatin, Y. Cao, “Method of Modeling Differential Vias,” White Paper, April 2010.
2. M.A.R. Gunston, “Microwave Transmission-Line Impedance Data,” Van Nostrand Reinhold Company LTD. 1972
3. Agilent ADS, Agilent EEsof EDA, 2009-Update 1
Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture. He is the founder of Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert,click here.