Faster Board Speeds Demand Constraint-Driven Design

Reading time ( words)

Do you still use Post-it Notes? Invented in 1979, this simple, yet incredibly powerful communication mechanism is still commonly found in engineering and design departments. Despite modern electronic communication, many companies still struggle to provide a replacement for their ease-of-use and versatility.

But, by changing the way an engineer designs electronics, by giving up the Post-it for passing requirements, change requests and constraints between engineers, design times can be shortened and product quality improved. Modern PCB design tools permit the definition of design constraints, including constraints relating to high-speed design and EMC, such as the topology of connections (routing pin sequence) or overshoot and timing budgets, for example.

These constraints become increasingly important as components and boards become faster and more complex. But it is hard to capture and use/obey these constraints consistently throughout the complete design process, bearing in mind that may contradict each other. The Post-it Note captures this idea particularly well. A brief sketch implicitly includes the constraints that the designer is working under, in a very concise form; however retaining and using this information later is extremely difficult.

Adaptive Design

Using these powerful constraint techniques can be a double-edged sword. While the design process is made much safer by including constraints, it is all too easy to over-constrain the design and make it impossible to complete routing and placement. Even paper design guidelines can make products uneconomic to produce unless a great deal of engineering knowledge is applied during the design. This means the design tool has to be adaptive—reacting to changes in the design as it progresses. Combining these elements is anything but trivial, but doing so allows the designer to converge on the optimum design in the first pass, rather than via multiple attempts.

In PCB design, attributes (or constraints) and rules have always existed, and designers have tried to achieve their design goals, especially with systems that are based around the raw attributes of the components in a design. But attributes (or properties) are essentially just data about the pins, components or tracking, while constraints are requirements that must be obeyed. Examples include the maximum delay, or an error marker, which must be flagged as functional or an operation may be at risk. These can simply be a function of the design attributes, but constraints are typically more complex nowadays and they sometimes relate to each other (e.g., in high-speed memory the relationship between the byte lanes and from the data/address signals to strobe and clock signals). Constraints must exist through the different stages of the design process, from schematic to placement to routing.

To read this entire article, which appeared in the May 2018 issue of Design007 Magazine, click here.


Suggested Items

3D Convergence of Multiboard PCB and IC Packaging Design

07/18/2018 | Bob Potock, Zuken
A new generation of 3D multiboard product-level design tools offer major improvements by managing multiboard placement in both 2D and 3D, and enabling co-design of the chip, package and board in a single environment. Multiboard design makes it possible to create and validate a design with any combination of system-on-chips (SOCs), packages, and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.

Dave Wiens Discusses Multi-board Design Techniques

07/09/2018 | Andy Shaughnessy, I-Connect007
For our multi-board design issue, I interviewed Dave Wiens, product marketing manager for Mentor, a Siemens business. We discussed how the multi-board design technique differs from laying out single boards, along with the planning, simulation and analysis processes required to design multi-board systems.

Paving the Way for 400Gb Ethernet and 5G

06/26/2018 | Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.

Copyright © 2018 I-Connect007. All rights reserved.