DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.
A new generation of 3D multiboard product-level design tools offer major improvements by managing multiboard placement in both 2D and 3D, and enabling co-design of the chip, package and board in a single environment. Multiboard design makes it possible to create and validate a design with any combination of system-on-chips (SOCs), packages, and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.
Flexible circuits are known by a few different names depending on one’s global location and language: flexible printed circuits, FPCs, flex circuits, flexi circuits, flexibles, bendables and a few others that are...
Susy Webb: Training the New Generation of Designers, a conversation with Susy Webb
Help Wanted: PCB Design Layout Specialist, by Mike Creeden, CID+, MIT
Mentor Preparing for Next-Gen PCB Designers, a conversation with Paul Musto
Where Have All the Designers Gone (and Who Will be Taking Their Place)? by Tim Haag
In With the New at Cadence, a conversation with Bryan LaPointe and Dan Fernsebner